System Verilog UVM based Verification IP for all major
HW simulators.



The X-STEP™ product family includes UVM-based Verification IP for HW simulation and emulation environments. This extends the unique protocol testing features of X-STEP™ HW products to RTL simulations.


X-STEP Verification IPs provide Actor-level functionality at the beginning of the product development process, the RTL development and verification phase. Protocols supported by X-STEP Verification IP include CPRI, OBSAI RP3, and JESD204. The Verification IP is designed and tested with RTL simulators from the major EDA tool vendors and have three parts: UVM connection and monitors for a simulation testbench, SystemVerilog Bus Functional Models (BFMs) with example test benches, and the very same C++ protocol framer core that is used in all X-STEP products. X-STEP Verification IPs provide an excellent starting point for system verification and validation as all tests are directly reusable with X-STEP Actor in later phases of the project.